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Refactors how components are triggered and refactors how ports are ordered (#60934)

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Co-authored-by: Watermelon914 <3052169-Watermelon914@users.noreply.gitlab.com>
This commit is contained in:
Watermelon914
2021-09-03 02:22:39 -07:00
committed by GitHub
co-authored by Watermelon914
parent a9cc1bc816
commit 126411f405
76 changed files with 265 additions and 429 deletions
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code/modules/wiremod/components/math/arithmetic.dm
+1 -5
View File
@@ -37,8 +37,7 @@
)
arithmetic_option = add_option_port("Arithmetic Option", component_options)
/obj/item/circuit_component/arithmetic/Initialize()
. = ..()
/obj/item/circuit_component/arithmetic/populate_ports()
arithmetic_ports = list()
for(var/port_id in 1 to input_port_amount)
var/letter = ascii2text(text2ascii("A") + (port_id-1))
@@ -47,9 +46,6 @@
output = add_output_port("Output", PORT_TYPE_NUMBER)
/obj/item/circuit_component/arithmetic/input_received(datum/port/input/port)
. = ..()
if(.)
return
var/list/ports = arithmetic_ports.Copy()
var/datum/port/input/first_port = popleft(ports)
code/modules/wiremod/components/math/comparison.dm
+1 -2
View File
@@ -23,7 +23,7 @@
)
comparison_option = add_option_port("Comparison Option", component_options)
/obj/item/circuit_component/compare/comparison/input_received(datum/port/input/port)
/obj/item/circuit_component/compare/comparison/pre_input_received(datum/port/input/port)
switch(comparison_option.value)
if(COMP_COMPARISON_EQUAL, COMP_COMPARISON_NOT_EQUAL)
if(current_type != PORT_TYPE_ANY)
@@ -35,7 +35,6 @@
current_type = PORT_TYPE_NUMBER
compare_ports[1].set_datatype(PORT_TYPE_NUMBER)
compare_ports[2].set_datatype(PORT_TYPE_NUMBER)
return ..()
/obj/item/circuit_component/compare/comparison/do_comparisons(list/ports)
code/modules/wiremod/components/math/length.dm
+1 -5
View File
@@ -14,16 +14,12 @@
var/datum/port/output/output
circuit_flags = CIRCUIT_FLAG_INPUT_SIGNAL|CIRCUIT_FLAG_OUTPUT_SIGNAL
/obj/item/circuit_component/length/Initialize()
. = ..()
/obj/item/circuit_component/length/populate_ports()
input_port = add_input_port("Input", PORT_TYPE_ANY)
output = add_output_port("Length", PORT_TYPE_NUMBER)
/obj/item/circuit_component/length/input_received(datum/port/input/port)
. = ..()
if(.)
return
output.set_output(length(input_port.value))
code/modules/wiremod/components/math/not.dm
+1 -5
View File
@@ -14,16 +14,12 @@
var/datum/port/output/result
circuit_flags = CIRCUIT_FLAG_INPUT_SIGNAL|CIRCUIT_FLAG_OUTPUT_SIGNAL
/obj/item/circuit_component/not/Initialize()
. = ..()
/obj/item/circuit_component/not/populate_ports()
input_port = add_input_port("Input", PORT_TYPE_ANY)
result = add_output_port("Result", PORT_TYPE_NUMBER)
/obj/item/circuit_component/not/input_received(datum/port/input/port)
. = ..()
if(.)
return
result.set_output(!input_port.value)
code/modules/wiremod/components/math/random.dm
+3 -7
View File
@@ -17,17 +17,13 @@
/// The result from the output
var/datum/port/output/output
/obj/item/circuit_component/random/Initialize()
. = ..()
minimum = add_input_port("Minimum", PORT_TYPE_NUMBER, FALSE)
maximum = add_input_port("Maximum", PORT_TYPE_NUMBER, FALSE)
/obj/item/circuit_component/random/populate_ports()
minimum = add_input_port("Minimum", PORT_TYPE_NUMBER, trigger = null)
maximum = add_input_port("Maximum", PORT_TYPE_NUMBER, trigger = null)
output = add_output_port("Output", PORT_TYPE_NUMBER)
/obj/item/circuit_component/random/input_received(datum/port/input/port)
. = ..()
if(.)
return
var/min_val = minimum.value || 0
var/max_val = maximum.value || 0