From 70bed45cc81c09a2ab72d532c562a013f63e1eb4 Mon Sep 17 00:00:00 2001
From: SkyratBot <59378654+SkyratBot@users.noreply.github.com>
Date: Sun, 30 May 2021 01:52:26 +0200
Subject: [PATCH] [MIRROR] Fixes AND/OR gates for Integrated Circuits (#6022)

* Fixes AND/OR gates ignoring a port if it has a null value but it is still connected to another port (#59348)

Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>

* Fixes AND/OR gates for Integrated Circuits

Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com>
Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>
---
 code/modules/wiremod/components/logic.dm | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/code/modules/wiremod/components/logic.dm b/code/modules/wiremod/components/logic.dm
index 02a37194279..acedb79613c 100644
--- a/code/modules/wiremod/components/logic.dm
+++ b/code/modules/wiremod/components/logic.dm
@@ -23,7 +23,7 @@ GLOBAL_LIST_INIT(comp_logic_options, list(
 	var/total_ports = 0
 	var/total_true_ports = 0
 	for(var/datum/port/input/port as anything in ports)
-		if(isnull(port.input_value))
+		if(isnull(port.input_value) && isnull(port.connected_port))
 			continue
 
 		total_ports += 1