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[MIRROR] Adds the ability to save/load circuits for admins. Adds the ability to duplicate modules in a round. (#7197)

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* Adds the ability to save/load circuits for admins. Adds the ability to duplicate modules in a round. (#60222)

Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>

* Adds the ability to save/load circuits for admins. Adds the ability to duplicate modules in a round.

* a

Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com>
Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>
Co-authored-by: Gandalf <jzo123@hotmail.com>
This commit is contained in:
SkyratBot
2021-07-28 23:28:01 +01:00
committed by GitHub
co-authored by Watermelon914 Watermelon914 Gandalf
parent c0bd3dd08a
commit 778c303215
25 changed files with 2433 additions and 1912 deletions
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code/modules/wiremod/components/abstract/module.dm
+59 -6
View File
@@ -18,7 +18,7 @@
var/port_limit = 10
/obj/item/integrated_circuit/module
var/obj/item/circuit_component/attached_module
var/obj/item/circuit_component/module/attached_module
/obj/item/integrated_circuit/module/ui_host(mob/user)
. = ..()
@@ -29,6 +29,18 @@
. = ..()
attached_module.display_name = new_name
/obj/item/integrated_circuit/module/load_component(type)
if(!attached_module)
return ..()
if(ispath(type, /obj/item/circuit_component/module_input))
return attached_module.input_component
if(ispath(type, /obj/item/circuit_component/module_output))
return attached_module.output_component
return ..()
/obj/item/integrated_circuit/module/Destroy()
attached_module = null
return ..()
@@ -88,7 +100,7 @@
input_component = new(internal_circuit)
input_component.attached_module = src
internal_circuit.add_component(input_component)
input_component.rel_x = 400
input_component.rel_x = 0
input_component.rel_y = 200
output_component = new(internal_circuit)
@@ -97,6 +109,49 @@
output_component.rel_x = 400
output_component.rel_y = 200
/obj/item/circuit_component/module/save_data_to_list(list/component_data)
. = ..()
component_data["integrated_circuit"] = internal_circuit.convert_to_json()
var/list/input_data = list()
for(var/datum/port/input/input_port as anything in input_ports)
input_data += list(list(
"name" = input_port.name,
"type" = input_port.datatype,
))
var/list/output_data = list()
for(var/datum/port/output/output_port as anything in output_ports)
output_data += list(list(
"name" = output_port.name,
"type" = output_port.datatype,
))
component_data["input_ports"] = input_data
component_data["output_ports"] = output_data
/obj/item/circuit_component/module/load_data_from_list(list/component_data)
. = ..()
var/list/input_ports = component_data["input_ports"]
for(var/list/port_data as anything in input_ports)
add_and_link_input_port(port_data["name"], port_data["type"])
var/list/output_ports = component_data["output_ports"]
for(var/list/port_data as anything in output_ports)
add_and_link_output_port(port_data["name"], port_data["type"])
if(component_data["integrated_circuit"])
internal_circuit.load_circuit_data(component_data["integrated_circuit"])
/obj/item/circuit_component/module/proc/add_and_link_input_port(name, type)
var/datum/port/new_port = add_input_port(name, type)
linked_ports[new_port] = input_component.add_output_port(name, type)
/obj/item/circuit_component/module/proc/add_and_link_output_port(name, type)
var/datum/port/new_port = output_component.add_input_port(name, type)
linked_ports[new_port] = add_output_port(name, type)
/obj/item/circuit_component/module/add_to(obj/item/integrated_circuit/added_to)
. = ..()
RegisterSignal(added_to, COMSIG_CIRCUIT_SET_CELL, .proc/handle_set_cell)
@@ -177,8 +232,7 @@
if("add_input_port")
if(length(input_ports) > port_limit)
return
var/datum/port/new_port = add_input_port("Input Port", PORT_TYPE_ANY)
linked_ports[new_port] = input_component.add_output_port("Input Port", PORT_TYPE_ANY)
add_and_link_input_port("Input Port", PORT_TYPE_ANY)
. = TRUE
if("remove_input_port")
var/port_id = text2num(params["port_id"])
@@ -192,8 +246,7 @@
if("add_output_port")
if(length(output_ports) > port_limit)
return
var/datum/port/new_port = output_component.add_input_port("Output Port", PORT_TYPE_ANY)
linked_ports[new_port] = add_output_port("Output Port", PORT_TYPE_ANY)
add_and_link_output_port("Output Port", PORT_TYPE_ANY)
. = TRUE
if("remove_output_port")
var/port_id = text2num(params["port_id"])