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[MIRROR] Refactors how components are triggered and refactors how ports are ordered (#7951)

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* Refactors how components are triggered and refactors how ports are ordered (#60934)

Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>

* Refactors how components are triggered and refactors how ports are ordered

Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com>
Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>
This commit is contained in:
SkyratBot
2021-09-03 15:02:48 +02:00
committed by GitHub
parent 94bc4b3a6a
commit af8c0d2977
76 changed files with 265 additions and 429 deletions
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code/modules/wiremod/components/string/textcase.dm
+1 -5
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@@ -27,15 +27,11 @@
)
textcase_options = add_option_port("Textcase Options", component_options)
/obj/item/circuit_component/textcase/Initialize()
. = ..()
/obj/item/circuit_component/textcase/populate_ports()
input_port = add_input_port("Input", PORT_TYPE_STRING)
output = add_output_port("Output", PORT_TYPE_STRING)
/obj/item/circuit_component/textcase/input_received(datum/port/input/port)
. = ..()
if(.)
return
var/value = input_port.value
if(isnull(value))