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[MIRROR] Refactors how components are triggered and refactors how ports are ordered (#7951)

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* Refactors how components are triggered and refactors how ports are ordered (#60934)

Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>

* Refactors how components are triggered and refactors how ports are ordered

Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com>
Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>
This commit is contained in:
SkyratBot
2021-09-03 14:02:48 +01:00
committed by GitHub
co-authored by Watermelon914 Watermelon914
parent 94bc4b3a6a
commit af8c0d2977
76 changed files with 265 additions and 429 deletions
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code/modules/wiremod/shell/controller.dm
+1 -2
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@@ -33,8 +33,7 @@
/// The entity output
var/datum/port/output/entity
/obj/item/circuit_component/controller/Initialize()
. = ..()
/obj/item/circuit_component/controller/populate_ports()
entity = add_output_port("User", PORT_TYPE_ATOM)
signal = add_output_port("Signal", PORT_TYPE_SIGNAL)
alt = add_output_port("Alternate Signal", PORT_TYPE_SIGNAL)