Commit Graph

5 Commits

Author SHA1 Message Date
SkyratBot
db78fbb47a [MIRROR] Adds Circuit variables (#7539)
* Adds Circuit variables (#60590)

Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>

* Adds Circuit variables

Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com>
Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>
2021-08-13 17:23:58 +01:00
SkyratBot
9e74cd4a03 [MIRROR] Input ports now connect to multiple output ports. Remove combiner. (#7505)
* Input ports now connect to multiple output ports. Remove combiner. (#60494)

* tgui bsod

* debug disconnections

* prelim

* recomment

* set_value -> put ._.

* DAMN IT

* reinsert subsystem

* prepare

* unditch signals

* remove combiner

* remove combiner some more

* how did router.dm get here? deleting.

* These two COMSIGS should be one.

* critical typo

* inline cast

* have your signals

* Have your set_input & set_output.

* make compile

* upgrade save/load to n-to-n-wires

* have your documentation

* have your unsafe proc

* pay no attention to the compile errors

* unlist the ref

* paste my for block back in ._.

* fix manual input

* oops pushed too soon

* Have your !port.connected_to?.length

Co-authored-by: Watermelon914 <37270891+Watermelon914@ users.noreply.github.com>

Co-authored-by: Watermelon914 <37270891+Watermelon914@ users.noreply.github.com>

* Input ports now connect to multiple output ports. Remove combiner.

Co-authored-by: Gurkenglas <gurkenglas@hotmail.de>
Co-authored-by: Watermelon914 <37270891+Watermelon914@ users.noreply.github.com>
2021-08-11 20:27:29 +01:00
SkyratBot
170863cfd7 [MIRROR] Circuit component descriptions and module names are now visible to the naked eye. (#7290)
* Circuit component descriptions and module names are now visible to the naked eye. (#60545)

* Circuit component descriptions and module names are now visible to the naked eye.

Co-authored-by: Gurkenglas <gurkenglas@hotmail.de>
2021-08-01 11:42:08 +01:00
SkyratBot
778c303215 [MIRROR] Adds the ability to save/load circuits for admins. Adds the ability to duplicate modules in a round. (#7197)
* Adds the ability to save/load circuits for admins. Adds the ability to duplicate modules in a round. (#60222)

Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>

* Adds the ability to save/load circuits for admins. Adds the ability to duplicate modules in a round.

* a

Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com>
Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>
Co-authored-by: Gandalf <jzo123@hotmail.com>
2021-07-28 23:28:01 +01:00
SkyratBot
b37a8b5ef0 [MIRROR] Circuit submodules (#6980)
* Circuit submodules (#60109)

Adds the module component that is basically a subroutine. Allows you to compact your logic into a bunch of functions.

* Circuit submodules

Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com>
2021-07-19 20:12:15 +12:00