* Integrated the component printer into the integrated circuit UI. You can now link integrated circuits to component printers (#62287)
Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>
* Integrated the component printer into the integrated circuit UI. You can now link integrated circuits to component printers
Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com>
Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>
* Adds 2 new signals, adds pre/postattack_secondary signals to circuit signal handler presets (+a proccall component fix) (#62233)
Adds COMSIG_ITEM_AFTERATTACK_SECONDARY and COMSIG_MOB_ITEM_AFTERATTACK_SECONDARY signals, which are both called by item/proc/afterattack_secondary.
Adds COMSIG_ITEM_PRE_ATTACK_SECONDARY and COMSIG_ITEM_AFTERATTACK_SECONDARY to the list of circuit signal handler presets.
The proc call, set var, and spawn atom components will resolve any weakrefs passed to them in their parameter port, seeing as the list literal component now converts datums into weakrefs.
* Adds 2 new signals, adds pre/postattack_secondary signals to circuit signal handler presets (+a proccall component fix)
Co-authored-by: Y0SH1M4S73R <legoboyo@earthlink.net>
* Adds a Datum port type for Admin Circuits (#61582)
Admin circuit components were limited in their utility due to the setvar, getvar, proccall, and signal handler components only being able to operate on atoms. I have improved them by adding the datum datatype, which is used exclusively by the aforementioned components in place of the atom datatype their target port currently uses. Furthermore, an option for the expected output type has been added to the getvar and proccall components. This option defaults to any.
* Adds a Datum port type for Admin Circuits
Co-authored-by: Y0SH1M4S73R <legoboyo@earthlink.net>
* Refactors how components are triggered and refactors how ports are ordered (#60934)
Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>
* Refactors how components are triggered and refactors how ports are ordered
Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com>
Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>
* Input ports now connect to multiple output ports. Remove combiner. (#60494)
* tgui bsod
* debug disconnections
* prelim
* recomment
* set_value -> put ._.
* DAMN IT
* reinsert subsystem
* prepare
* unditch signals
* remove combiner
* remove combiner some more
* how did router.dm get here? deleting.
* These two COMSIGS should be one.
* critical typo
* inline cast
* have your signals
* Have your set_input & set_output.
* make compile
* upgrade save/load to n-to-n-wires
* have your documentation
* have your unsafe proc
* pay no attention to the compile errors
* unlist the ref
* paste my for block back in ._.
* fix manual input
* oops pushed too soon
* Have your !port.connected_to?.length
Co-authored-by: Watermelon914 <37270891+Watermelon914@ users.noreply.github.com>
Co-authored-by: Watermelon914 <37270891+Watermelon914@ users.noreply.github.com>
* Input ports now connect to multiple output ports. Remove combiner.
Co-authored-by: Gurkenglas <gurkenglas@hotmail.de>
Co-authored-by: Watermelon914 <37270891+Watermelon914@ users.noreply.github.com>
SkyratBot