Commit Graph

5 Commits

Author SHA1 Message Date
Watermelon914
05ede8dc30 Adds Circuit variables (#60590)
Co-authored-by: Watermelon914 <3052169-Watermelon914@users.noreply.gitlab.com>
2021-08-12 18:30:50 -07:00
Gurkenglas
e0fad671fd Input ports now connect to multiple output ports. Remove combiner. (#60494)
* tgui bsod

* debug disconnections

* prelim

* recomment

* set_value -> put ._.

* DAMN IT

* reinsert subsystem

* prepare

* unditch signals

* remove combiner

* remove combiner some more

* how did router.dm get here? deleting.

* These two COMSIGS should be one.

* critical typo

* inline cast

* have your signals

* Have your set_input & set_output.

* make compile

* upgrade save/load to n-to-n-wires

* have your documentation

* have your unsafe proc

* pay no attention to the compile errors

* unlist the ref

* paste my for block back in ._.

* fix manual input

* oops pushed too soon

* Have your !port.connected_to?.length

Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com>

Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com>
2021-08-11 18:48:29 +03:00
Gurkenglas
aa018a857a Circuit component descriptions and module names are now visible to the naked eye. (#60545) 2021-07-31 21:19:43 -07:00
Watermelon914
548f924c21 Adds the ability to save/load circuits for admins. Adds the ability to duplicate modules in a round. (#60222)
Co-authored-by: Watermelon914 <3052169-Watermelon914@users.noreply.gitlab.com>
2021-07-28 14:26:50 -07:00
Watermelon914
5a21e2e64c Circuit submodules (#60109)
Adds the module component that is basically a subroutine. Allows you to compact your logic into a bunch of functions.
2021-07-17 01:05:57 -03:00