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af8c0d2977
* Refactors how components are triggered and refactors how ports are ordered (#60934) Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com> * Refactors how components are triggered and refactors how ports are ordered Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com> Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>
55 lines
1.5 KiB
Plaintext
55 lines
1.5 KiB
Plaintext
/**
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* # Compare Component
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*
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* Abstract component to build conditional components
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*/
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/obj/item/circuit_component/compare
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display_name = "Compare"
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/// The amount of input ports to have
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var/input_port_amount = 4
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/// The trigger for the true/false signals
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var/datum/port/input/compare
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/// Signals sent on compare
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var/datum/port/output/true
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var/datum/port/output/false
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/// The result from the output
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var/datum/port/output/result
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var/list/datum/port/input/compare_ports = list()
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/obj/item/circuit_component/compare/populate_ports()
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for(var/port_id in 1 to input_port_amount)
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var/letter = ascii2text(text2ascii("A") + (port_id-1))
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compare_ports += add_input_port(letter, PORT_TYPE_ANY)
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populate_custom_ports()
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compare = add_input_port("Compare", PORT_TYPE_SIGNAL)
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true = add_output_port("True", PORT_TYPE_SIGNAL)
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false = add_output_port("False", PORT_TYPE_SIGNAL)
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result = add_output_port("Result", PORT_TYPE_NUMBER)
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/**
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* Used by derivatives to load their own ports in for custom use.
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*/
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/obj/item/circuit_component/compare/proc/populate_custom_ports()
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return
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/obj/item/circuit_component/compare/input_received(datum/port/input/port)
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var/logic_result = do_comparisons(compare_ports)
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if(COMPONENT_TRIGGERED_BY(compare, port))
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if(logic_result)
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true.set_output(COMPONENT_SIGNAL)
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else
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false.set_output(COMPONENT_SIGNAL)
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result.set_output(logic_result)
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/// Do the comparisons and return a result
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/obj/item/circuit_component/compare/proc/do_comparisons(list/ports)
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return FALSE
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