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af8c0d2977
* Refactors how components are triggered and refactors how ports are ordered (#60934) Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com> * Refactors how components are triggered and refactors how ports are ordered Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com> Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>
26 lines
635 B
Plaintext
26 lines
635 B
Plaintext
/**
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* # Logic Component
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*
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* General logic unit with AND OR capabilities
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*/
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/obj/item/circuit_component/not
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display_name = "Not"
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desc = "A component that inverts its input."
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/// The input port
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var/datum/port/input/input_port
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/// The result from the output
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var/datum/port/output/result
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circuit_flags = CIRCUIT_FLAG_INPUT_SIGNAL|CIRCUIT_FLAG_OUTPUT_SIGNAL
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/obj/item/circuit_component/not/populate_ports()
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input_port = add_input_port("Input", PORT_TYPE_ANY)
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result = add_output_port("Result", PORT_TYPE_NUMBER)
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/obj/item/circuit_component/not/input_received(datum/port/input/port)
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result.set_output(!input_port.value)
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