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* Integrated Circuits (Wiremod) * AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com> Co-authored-by: Gandalf <jzo123@hotmail.com>
34 lines
871 B
Plaintext
34 lines
871 B
Plaintext
/**
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* # Dummy Component
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*
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* Dummy component that does nothing, only for debugging purposes
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*
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* Has two input and output ports that do nothing
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*/
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/obj/item/circuit_component/dummy
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display_name = "Dummy Component"
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/// The input ports of the dummy component
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var/datum/port/input/receive1
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var/datum/port/input/receive2
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/// The output ports of the dummy component
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var/datum/port/output/output1
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var/datum/port/output/output2
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/obj/item/circuit_component/dummy/Initialize()
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. = ..()
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receive1 = add_input_port("Receive 1", PORT_TYPE_ANY)
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receive2 = add_input_port("Receive 2", PORT_TYPE_ANY)
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output1 = add_output_port("Output 1", PORT_TYPE_NUMBER)
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output2 = add_output_port("Output 2", PORT_TYPE_NUMBER)
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/obj/item/circuit_component/dummy/Destroy()
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// Cleaned up in parent proc
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receive1 = null
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receive2 = null
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output1 = null
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output2 = null
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return ..()
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