Watermelon914 1a507d23ed Refactors how circuit size is calculated. Fixed module circuit size not taking up capacity equal to the amount of circuit components inside of it. (#61554) ...

Co-authored-by: Watermelon914 <3052169-Watermelon914@users.noreply.gitlab.com>

2021-09-30 11:09:42 -07:00

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clock.dm

Refactors how components are triggered and refactors how ports are ordered (#60934)

2021-09-03 02:22:39 -07:00

delay.dm

Adds the interrupt signal to the delay component, reorganises BCI files and circuit code improvements (#61393)

2021-09-19 00:21:52 -07:00

getter.dm

Refactors how circuit size is calculated. Fixed module circuit size not taking up capacity equal to the amount of circuit components inside of it. (#61554)

2021-09-30 11:09:42 -07:00

router.dm

Refactors how components are triggered and refactors how ports are ordered (#60934)

2021-09-03 02:22:39 -07:00

setter.dm

Refactors how circuit size is calculated. Fixed module circuit size not taking up capacity equal to the amount of circuit components inside of it. (#61554)

2021-09-30 11:09:42 -07:00

typecast.dm

Refactors how components are triggered and refactors how ports are ordered (#60934)

2021-09-03 02:22:39 -07:00

typecheck.dm

Input ports now connect to multiple output ports. Remove combiner. (#60494)

2021-08-11 18:48:29 +03:00