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cyberpresidentvanellope/GS13-Citadel
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mirror of https://github.com/evilew/GS13-Citadel.git synced 2026-08-19 03:07:03 +01:00
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bbdcff81bb7158237e69869c032f1e018874f277
GS13-Citadel/code/modules/research/designs
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History
CitadelStationBot 4da7414339 Old ore processor cleanup
2017-04-29 03:46:03 -05:00
..
AI_module_designs.dm
some modules things
2017-02-08 00:06:03 -06:00
autolathe_designs.dm
/tg/ 4/14 (#367)
2017-04-14 23:28:04 -05:00
biogenerator_designs.dm
Tg patch branch to master (#192)
2017-02-03 05:56:14 -06:00
comp_board_designs.dm
Bleeding edgy refresh (#303)
2017-03-21 11:44:10 -05:00
computer_part_designs.dm
Tg patch branch to master (#192)
2017-02-03 05:56:14 -06:00
limbgrower_designs.dm
Tg patch branch to master (#192)
2017-02-03 05:56:14 -06:00
machine_designs.dm
April sync (#360)
2017-04-13 23:37:00 -05:00
mecha_designs.dm
Overhauls and 2/28 sync (#244)
2017-02-28 09:30:49 -06:00
mechfabricator_designs.dm
April sync (#360)
2017-04-13 23:37:00 -05:00
medical_designs.dm
Hotfixes for March 3, 2017 (#260)
2017-03-03 15:15:42 -05:00
power_designs.dm
Overhauls and 2/28 sync (#244)
2017-02-28 09:30:49 -06:00
smelting_designs.dm
Old ore processor cleanup
2017-04-29 03:46:03 -05:00
stock_parts_designs.dm
Overhauls and 2/28 sync (#244)
2017-02-28 09:30:49 -06:00
telecomms_designs.dm
initial commit - cross reference with 5th port - obviously has compile errors
2016-07-03 02:17:19 -05:00
weapon_designs.dm
April sync (#360)
2017-04-13 23:37:00 -05:00
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