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SandPoot
2022-04-06 18:41:31 -03:00
parent 4c3fa08cdf
commit 586a035132
881 changed files with 1599 additions and 1599 deletions
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code/modules/wiremod/components/math/length.dm
+1 -1
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@@ -14,7 +14,7 @@
var/datum/port/output/output
circuit_flags = CIRCUIT_FLAG_INPUT_SIGNAL|CIRCUIT_FLAG_OUTPUT_SIGNAL
/obj/item/circuit_component/length/Initialize()
/obj/item/circuit_component/length/Initialize(mapload)
. = ..()
input_port = add_input_port("Input", PORT_TYPE_ANY)