Fixing empty new lines on circuit examines.

This commit is contained in:
Ghommie
2020-04-24 23:44:07 +02:00
parent debbd3edab
commit ca2d4ae28f
2 changed files with 7 additions and 3 deletions
@@ -79,7 +79,9 @@
for(var/I in assembly_components)
var/obj/item/integrated_circuit/IC = I
. += IC.external_examine(user)
var/text = IC.external_examine(user)
if(text)
. += text
if(opened)
interact(user)