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[MIRROR] Fixes AND/OR gates for Integrated Circuits (#6022)

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* Fixes AND/OR gates ignoring a port if it has a null value but it is still connected to another port (#59348)

Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>

* Fixes AND/OR gates for Integrated Circuits

Co-authored-by: Watermelon914 <37270891+Watermelon914@users.noreply.github.com>
Co-authored-by: Watermelon914 <3052169-Watermelon914@ users.noreply.gitlab.com>
This commit is contained in:
SkyratBot
2021-05-30 00:52:26 +01:00
committed by GitHub
co-authored by Watermelon914 Watermelon914
parent c89ef19020
commit 70bed45cc8
1 changed files with 1 additions and 1 deletions
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code/modules/wiremod/components/logic.dm
+1 -1
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@@ -23,7 +23,7 @@ GLOBAL_LIST_INIT(comp_logic_options, list(
var/total_ports = 0
var/total_true_ports = 0
for(var/datum/port/input/port as anything in ports)
if(isnull(port.input_value))
if(isnull(port.input_value) && isnull(port.connected_port))
continue
total_ports += 1