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Fixes AND/OR gates ignoring a port if it has a null value but it is still connected to another port (#59348)

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Co-authored-by: Watermelon914 <3052169-Watermelon914@users.noreply.gitlab.com>
This commit is contained in:
Watermelon914
2021-05-29 04:59:24 +01:00
committed by GitHub
parent 5a8c9f8274
commit fa4484d2fd
1 changed files with 1 additions and 1 deletions
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code/modules/wiremod/components/logic.dm
+1 -1
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@@ -23,7 +23,7 @@ GLOBAL_LIST_INIT(comp_logic_options, list(
var/total_ports = 0
var/total_true_ports = 0
for(var/datum/port/input/port as anything in ports)
if(isnull(port.input_value))
if(isnull(port.input_value) && isnull(port.connected_port))
continue
total_ports += 1