Merge pull request #2246 from Citadel-Station-13/upstream-merge-29647
[MIRROR] Fixes SendSignal()
This commit is contained in:
@@ -1,22 +1,35 @@
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/datum/component
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var/enabled = TRUE
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var/dupe_mode = COMPONENT_DUPE_HIGHLANDER
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var/dupe_type
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var/list/signal_procs
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var/datum/parent
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/datum/component/New(datum/P, ...)
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parent = P
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var/list/arguments = args.Copy()
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arguments.Cut(1, 2)
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Initialize(arglist(arguments))
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var/dm = dupe_mode
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if(dm != COMPONENT_DUPE_ALLOWED)
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var/datum/component/old = P.GetExactComponent(type)
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if(old)
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switch(dm)
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if(COMPONENT_DUPE_HIGHLANDER)
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InheritComponent(old, FALSE)
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qdel(old)
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if(COMPONENT_DUPE_UNIQUE)
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old.InheritComponent(src, TRUE)
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qdel(src)
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return
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var/dt = dupe_type
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var/datum/component/old
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if(!dt)
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old = P.GetExactComponent(type)
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else
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old = P.GetComponent(dt)
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switch(dm)
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if(COMPONENT_DUPE_UNIQUE)
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old.InheritComponent(src, TRUE)
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parent = null //prevent COMPONENT_REMOVING signal
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qdel(src)
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return
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if(COMPONENT_DUPE_HIGHLANDER)
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InheritComponent(old, FALSE)
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qdel(old)
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//let the others know
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P.SendSignal(COMSIG_COMPONENT_ADDED, src)
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//lazy init the parent's dc list
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@@ -26,7 +39,7 @@
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//set up the typecache
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var/our_type = type
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for(var/I in _GetInverseTypeListExceptRoot(our_type))
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for(var/I in _GetInverseTypeList(our_type))
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var/test = dc[I]
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if(test) //already another component of this type here
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var/list/components_of_type
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@@ -50,7 +63,8 @@
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else //only component of this type, no list
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dc[I] = src
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parent = P
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/datum/component/proc/Initialize(...)
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return
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/datum/component/Destroy()
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enabled = FALSE
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@@ -66,7 +80,7 @@
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if(P)
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var/list/dc = P.datum_components
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var/our_type = type
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for(var/I in _GetInverseTypeListExceptRoot(our_type))
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for(var/I in _GetInverseTypeList(our_type))
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var/list/components_of_type = dc[I]
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if(islist(components_of_type)) //
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var/list/subtracted = components_of_type - src
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@@ -110,23 +124,35 @@
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/datum/component/proc/OnTransfer(datum/new_parent)
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return
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/datum/component/proc/_GetInverseTypeListExceptRoot(our_type_cached)
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var/datum/component/current_type = our_type_cached
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. = list()
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/datum/component/proc/AfterComponentActivated()
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return
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/datum/component/proc/_GetInverseTypeList(current_type)
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. = list(current_type)
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while (current_type != /datum/component)
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. += current_type
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current_type = type2parent(current_type)
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. += current_type
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/datum/proc/SendSignal(sigtype, ...)
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var/list/comps = datum_components
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. = FALSE
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for(var/I in comps)
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var/datum/component/C = I
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if(!C.enabled)
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continue
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if(C.ReceiveSignal(arglist(args)))
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if(!comps)
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return
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var/target = comps[/datum/component]
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if(!islist(target))
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var/datum/component/C = target
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if(C.enabled && C.ReceiveSignal(arglist(args)))
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ComponentActivated(C)
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. = TRUE
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C.AfterComponentActivated()
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return TRUE
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else
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for(var/I in target)
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var/datum/component/C = I
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if(!C.enabled)
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continue
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if(C.ReceiveSignal(arglist(args)))
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ComponentActivated(C)
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. = TRUE
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/datum/proc/ComponentActivated(datum/component/C)
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return
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@@ -165,6 +191,11 @@
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var/datum/component/C = new nt(arglist(args))
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return QDELING(C) ? GetComponent(new_type) : C
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/datum/proc/LoadComponent(component_type, ...)
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. = GetComponent(component_type)
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if(!.)
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return AddComponent(arglist(args))
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/datum/proc/TakeComponent(datum/component/C)
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if(!C)
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return
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@@ -1,18 +1 @@
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diff a/code/datums/components/component.dm b/code/datums/components/component.dm (rejected hunks)
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@@ -22,8 +22,7 @@
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//lazy init the parent's dc list
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var/list/dc = P.datum_components
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if(!dc)
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- dc = list()
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- P.datum_components = dc
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+ P.datum_components = dc = list()
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//set up the typecache
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var/our_type = type
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@@ -179,4 +178,4 @@
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helicopter.SendSignal(COMSIG_COMPONENT_REMOVING, C)
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C.OnTransfer(src)
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C.parent = src
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- SendSignal(COMSIG_COMPONENT_ADDED, C)
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\ No newline at end of file
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+ SendSignal(COMSIG_COMPONENT_ADDED, C)
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-
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