Update component.dm
This commit is contained in:
LetterJay
GitHub
@@ -26,7 +26,7 @@
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//set up the typecache
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var/our_type = type
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for(var/I in _GetInverseTypeList(our_type))
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for(var/I in _GetInverseTypeListExceptRoot(our_type))
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var/test = dc[I]
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if(test) //already another component of this type here
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var/list/components_of_type
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@@ -66,7 +66,7 @@
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if(P)
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var/list/dc = P.datum_components
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var/our_type = type
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for(var/I in _GetInverseTypeList(our_type))
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for(var/I in _GetInverseTypeListExceptRoot(our_type))
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var/list/components_of_type = dc[I]
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if(islist(components_of_type)) //
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var/list/subtracted = components_of_type - src
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@@ -110,226 +110,25 @@
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/datum/component/proc/OnTransfer(datum/new_parent)
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return
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/datum/component/proc/AfterComponentActivated()
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return
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/datum/component/proc/_GetInverseTypeList(current_type)
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. = list(current_type)
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/datum/component/proc/_GetInverseTypeListExceptRoot(our_type_cached)
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var/datum/component/current_type = our_type_cached
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. = list()
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while (current_type != /datum/component)
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current_type = type2parent(current_type)
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. += current_type
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current_type = type2parent(current_type)
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/datum/var/list/datum_components //special typecache of /datum/component
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/datum/proc/SendSignal(sigtype, ...)
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var/list/comps = datum_components
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. = FALSE
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if(!comps)
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return
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var/target = comps[/datum/component]
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if(!islist(target))
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var/datum/component/C = target
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if(C.enabled && C.ReceiveSignal(arglist(args)))
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for(var/I in comps)
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var/datum/component/C = I
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if(!C.enabled)
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continue
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if(C.ReceiveSignal(arglist(args)))
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ComponentActivated(C)
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C.AfterComponentActivated()
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return TRUE
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else
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for(var/I in target)
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var/datum/component/C = I
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if(!C.enabled)
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continue
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if(C.ReceiveSignal(arglist(args)))
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ComponentActivated(C)
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. = TRUE
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/datum/proc/ComponentActivated(datum/component/C)
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return
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/datum/proc/GetComponent(c_type)
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var/list/dc = datum_components
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if(!dc)
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return null
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. = dc[c_type]
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if(islist(.))
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return .[1]
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/datum/proc/GetExactComponent(c_type)
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var/list/dc = datum_components
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if(!dc)
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return null
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var/datum/component/C = dc[c_type]
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if(C)
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if(islist(C))
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C = C[1]
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if(C.type == c_type)
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return C
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return null
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/datum/proc/GetComponents(c_type)
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var/list/dc = datum_components
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if(!dc)
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return null
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. = dc[c_type]
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if(!islist(.))
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return list(.)
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/datum/proc/AddComponent(new_type, ...)
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var/nt = new_type
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args[1] = src
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var/datum/component/C = new nt(arglist(args))
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return QDELING(C) ? GetComponent(new_type) : C
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/datum/proc/TakeComponent(datum/component/C)
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if(!C)
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return
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var/datum/helicopter = C.parent
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if(helicopter == src)
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//wat
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return
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C._RemoveNoSignal()
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helicopter.SendSignal(COMSIG_COMPONENT_REMOVING, C)
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C.OnTransfer(src)
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C.parent = src
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SendSignal(COMSIG_COMPONENT_ADDED, C)
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/datum/component
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var/enabled = TRUE
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var/dupe_mode = COMPONENT_DUPE_HIGHLANDER
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var/list/signal_procs
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var/datum/parent
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/datum/component/New(datum/P, ...)
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var/dm = dupe_mode
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if(dm != COMPONENT_DUPE_ALLOWED)
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var/datum/component/old = P.GetExactComponent(type)
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if(old)
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switch(dm)
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if(COMPONENT_DUPE_HIGHLANDER)
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InheritComponent(old, FALSE)
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qdel(old)
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if(COMPONENT_DUPE_UNIQUE)
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old.InheritComponent(src, TRUE)
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qdel(src)
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return
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P.SendSignal(COMSIG_COMPONENT_ADDED, src)
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//lazy init the parent's dc list
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var/list/dc = P.datum_components
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if(!dc)
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P.datum_components = dc = list()
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//set up the typecache
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var/our_type = type
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for(var/I in _GetInverseTypeList(our_type))
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var/test = dc[I]
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if(test) //already another component of this type here
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var/list/components_of_type
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if(!islist(test))
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components_of_type = list(test)
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dc[I] = components_of_type
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else
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components_of_type = test
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if(I == our_type) //exact match, take priority
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var/inserted = FALSE
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for(var/J in 1 to components_of_type.len)
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var/datum/component/C = components_of_type[J]
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if(C.type != our_type) //but not over other exact matches
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components_of_type.Insert(J, I)
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inserted = TRUE
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break
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if(!inserted)
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components_of_type += src
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else //indirect match, back of the line with ya
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components_of_type += src
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else //only component of this type, no list
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dc[I] = src
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parent = P
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/datum/component/Destroy()
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enabled = FALSE
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var/datum/P = parent
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if(P)
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_RemoveNoSignal()
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P.SendSignal(COMSIG_COMPONENT_REMOVING, src)
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LAZYCLEARLIST(signal_procs)
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return ..()
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/datum/component/proc/_RemoveNoSignal()
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var/datum/P = parent
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if(P)
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var/list/dc = P.datum_components
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var/our_type = type
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for(var/I in _GetInverseTypeList(our_type))
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var/list/components_of_type = dc[I]
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if(islist(components_of_type)) //
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var/list/subtracted = components_of_type - src
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if(subtracted.len == 1) //only 1 guy left
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dc[I] = subtracted[1] //make him special
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else
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dc[I] = subtracted
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else //just us
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dc -= I
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if(!dc.len)
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P.datum_components = null
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parent = null
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/datum/component/proc/RegisterSignal(sig_type, proc_on_self, override = FALSE)
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if(QDELETED(src))
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return
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var/list/procs = signal_procs
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if(!procs)
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procs = list()
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signal_procs = procs
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if(!override)
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. = procs[sig_type]
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if(.)
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stack_trace("[sig_type] overridden. Use override = TRUE to suppress this warning")
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procs[sig_type] = CALLBACK(src, proc_on_self)
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/datum/component/proc/ReceiveSignal(sigtype, ...)
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var/list/sps = signal_procs
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var/datum/callback/CB = LAZYACCESS(sps, sigtype)
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if(!CB)
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return FALSE
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var/list/arguments = args.Copy()
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arguments.Cut(1, 2)
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return CB.InvokeAsync(arglist(arguments))
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/datum/component/proc/InheritComponent(datum/component/C, i_am_original)
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return
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/datum/component/proc/OnTransfer(datum/new_parent)
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return
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/datum/component/proc/AfterComponentActivated()
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return
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/datum/component/proc/_GetInverseTypeList(current_type)
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. = list(current_type)
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while (current_type != /datum/component)
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current_type = type2parent(current_type)
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. += current_type
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/datum/proc/SendSignal(sigtype, ...)
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var/list/comps = datum_components
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. = FALSE
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if(!comps)
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return
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var/target = comps[/datum/component]
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if(!islist(target))
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var/datum/component/C = target
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if(C.enabled && C.ReceiveSignal(arglist(args)))
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ComponentActivated(C)
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C.AfterComponentActivated()
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return TRUE
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else
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for(var/I in target)
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var/datum/component/C = I
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if(!C.enabled)
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continue
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if(C.ReceiveSignal(arglist(args)))
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ComponentActivated(C)
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. = TRUE
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. = TRUE
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/datum/proc/ComponentActivated(datum/component/C)
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return
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